The invention comprises a method for connecting a processor to an ASIC, in which method the processor generates control signals employed when data is read from and written to the ASIC, and in which method the control signals generated by the processor are received, and read and write signals are generated on the basis of the received control signals.
The invention also comprises an arrangement for connecting a processor to an ASIC, which processor generates control signals employed when data is read from and written to the ASIC, which arrangement comprises means for receiving control signals from the processor and generating read and write signals on the basis of the received control signals
In electronic equipment, a processor environment is used where the processor is integrated to an external process or a component, such as an ASIC (Application Specific Integrated Circuit). Integration is accomplished by means of different input and output circuits, such as flip-flops. Integration also comprises different types of bus architectures for transmitting signals. The signals to be transmitted can include for example data, control or state signals.
In the processor environment, the signals are usually processed in a number of different components operating in synchronous or asynchronous mode. Processing in different components requires the components to be interconnected. However, interconnecting the components is not a simple task, since the signals usually call for accurate timing. Connecting for example the ASIC to a data bus in a digital DPS processor causes timing problems and thus complicates the transmission and processing of signals. For example communication frequency, control signals, bus architecture and different signal levels must be taken into account when interconnecting the components. Especially high frequency operation of the components brings about problems in signal timing.
The data bus of the processor is controlled by different control signals. Data is written to and read from the data bus by means of said control signals. The extremely accurate timing of the control signals is important so that the operations would take place at a desired moment. However, generating and timing the control signals is difficult. Timing problems have been solved by employing different types of interface architectures between the circuits to be interconnected. The interface architectures have been synchronous. Prior art interface architecture solutions have only partially solved the timing problems arising during the write and read operation.
Different types of synchronous flip-flops, i.e. FF solutions have been employed between the DSP processor and the ASIC. In addition, an OR element signal has been generated from the signals arriving from the processor to the ASIC, the OR element signal being employed as a clock signal for ASIC data and address registers. The flip-flops employed in the solution have been synchronized to the clock signal supplied by the processor. If for some reason the synchronization has been lost, the signals have reached a condition referred to as metastability. Signals in the metastabile state are unstable causing unpredictable and unwanted operations.
GB-A-2217064 describes a multiprocessor system comprising at least two asynchronous processors co-processing data. In the system, the processors perform handshaking implemented by means of an asynchronous state machine. The processors expect however a response of some kind from one another during the handshaking.
U.S. Pat. No. 5,339,395 describes an interface arrangement employed in a data transmission between a peripheral equipment and the data bus of a processor. The processor performs retrieval operations by fetching data from the memory on the basis of an address. The interface can comprise both synchronous and asynchronous modes of operation. The solution presented in the prior art document employs however a state machine changing its state on the basis of the received clock signal.
EP 744684 presents a solution for an ASIC bus interface. The bus interface enables that the clock signals can be connected between the ASIC and the processor in real time. The solution comprises a master state machine and several synchronizing state machines. The arrangement comprises however a clock generator generating clock signals for each synchronizing state machine.
The object of the present invention is to implement an arrangement that can be employed between a DSP processor and an ASIC enabling the elimination of timing problems involved in a write and read operation phase.
This object is achieved by the method presented in the preamble characterized by receiving the control signals and generating the read and write signals by an asynchronous state machine changing its state on the basis of the received control signals without a synchronizing clock signal being supplied to the state machine.
This object is also achieved by the arrangement presented in the preamble characterized in that the means are implemented by an asynchronous state machine changing its state on the basis of the received control signals, and that the means change their state without the need of a synchronizing clock signal.
The arrangement of the invention provides considerable advantages. The arrangement uses the asynchronous state machine generating the write and read signals by means of the control signals without any timing problems. The elimination of the timing problems enables the data always to be written to and read from the desired destination. The arrangement of the invention enables different clock signals to be used in the processor and the ASIC. Different clock signals enable for example the processor to be updated without causing problems to the ASIC operation.